Digital filter

ABSTRACT

A digital filter for a plural digitally expressed pulse code modulated (PCM) signal utilizes a storage register to retain several samples of the signal and obviates the need for digital multiplication circuits by using a delta coding for the filter coefficients. Processing steps are at a multiple of the sampling rate and at each step, the value of one stored sample is combined additively or subtractively with previously stored sample values as determined by stored delta coefficient values. The summed values are periodically transmitted as output samples of a filtered PCM signal.

GENERAL DESCRIPTION AND OBJECTS

This invention relates to a type of digital filter wherein the filtercoefficients needed to provide the desired impulse response are deltacoded.

When a signal x(t) passes through a filter having an impulse responseh(t), an output signal y(t) is obtained, which is the result of aconvolution operation defined by the following expression: ##EQU1##WHERE τ IS AN INTEGRATION VARIABLE.

An approximate value of signal y(t) can be derived from expression (1)by sampling functions h(t) and x(t) at regular intervals, for exampleevery T seconds. Expression (1) then becomes: ##EQU2## this value ofy(t) being within one attenuation coefficient 1/T of the correct value.

It will be seen that while expression (1) enables a determination of thevalue of y(t) at any time, expression (2) can only be used to provide adiscontinuous series of the values of the signal, that is, the values ofthe function of y(t) taken at regular intervals such as T. Accordingly,if we call h_(O), h₁, h₂ . . . h_(n) the values of h(NT) for N = 0, 1,2, . . . t/T we may state that the value of the sample of y at anyinstant t_(O) satisfies the expression:

    y.sub.(t.sbsb.0) = h.sub.O.sup.. x.sub.(t.sbsb.0) + h.sub.1.sup.. x.sub.(t.sbsb.0.sub.-T) + h.sub.2.sup.. x.sub.(t.sbsb.0.sub.-2T) +. . . +h.sub.n.sup.. x.sub.(t.sbsb.0.sub.-nT)                   ( 3)

the values h_(O), h₁, . . . h_(n) are the coefficients of the impulseresponse of the filter and x.sub.(.sbsb.0), x.sub.(t.sbsb.0_(-T)), . . ., x.sub.(t.sbsb.0_(-nT)) represent the value of the samples of thesignal to be filtered at instants t_(O), t_(o) -T, . . . t_(O) -nT.

A digital filter can therefore be defined as a device which determinesthe values of samples of the output signal y(t) by weighting n+1successive samples of the input signal x(t), using weightingcoefficients which are determined by sampling the desired impulseresponse at the sampling times, and by accumulating the results soobtained.

In order that the advantages of the present invention may be more fullyset out, the effects of the sampling process are briefly discussedhereafter. The sampling theorem shows that such a process results in amodification of the frequency spectrum of the signal being sampled. Thespectrum of the original signal is found, subsequent to sampling, aboveand below both the fundamental and each of the harmonics of the samplingfrequency. Accordingly, unless suitable precautions are taken, thevarious appearances of this spectrum may interfere with each other,thereby altering the output signal. In other words, the original signalwould not be recovered at the output of the sampler. Since the signalobtained at the filter output consists of samples, its spectrum willhave a comb-like form. To convert this signal to a continuous analogform, it is theoretically sufficient to cause it to pass through alow-pass filter, the cost of the filter being a function of the degreeof precision required. If the lobes of the spectrum of the signal whichis applied to the low-pass filter are sufficiently spaced from eachother, the low-pass filter can be of a very simple type. This shows thatthe higher the signal sampling frequency, the easier is the finalconversion of the signal to a filtered analog form. Since theconvolution operation in the time domain (expression (1) above) leads toa product in the frequency domain, if the spectrum of at least one ofthe sampled terms h(t) or x(t) comprises widely spaced lobes, so willthe spectrum of the sampled output signal y(t), and this will facilitateits conversion to an analog form.

One of the features of the well-known delta coding scheme is that itinvolves the use of a high sampling frequency. This type of coding istherefore particularly attractive from the standpoint of digitalfiltering. Many descriptions of such filters are available in the priorart. Reference is made in this connection to French Pat. No. 70 40291filed on Oct. 29, 1970 by the same assignee and entitled: "Filtredigital d'une Information en code delta" corresponding to U.S. Pat. No.3,822,404, issued July 2, 1974 to Alain Crosier et al. and to a paperentitled "A New Approach to the Realization of non-Recursive DigitalFilters" by Abraham Peled and Bede Liu in the IEEE Transactions on Audioand Electroacoustics, Vol. AU21, No. 6, December 1973. In both of thesereferences, the input signal x(t) is in a delta coded form while thefilter coefficients are binarily or PCM coded. In addition to theadvantages mentioned above, the use of the delta coding scheme entails asimplification of the mathematical operations required to evaluateexpression (3) since the values of the samples of x(t) can only be equalto +1 or -1. Also, the fact that the output signal is obtained at thehigh delta sampling frequency results in that signal beingquasi-continuous and better defined. However, this concept of filteringa delta modulated signal presents some disadvantages. When severaloperations, some of which require operations on samples of the signal inits binary coding scheme, are to be sequentially performed on signalx(t), such operations may not take place before the signal reaches thefilter or after it has left the filter unless intermediate recodingoperations are carried out to convert the signal from delta to PCMmodulation. In a signal processing system, such disadvantages mayoutweigh the above-mentioned advantages of the delta filtering method.

It is then the object of the present invention to provide a digitalfilter which allows the use of a PCM coded input signal x(t) whileretaining the advantages of the delta filtering scheme.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

DRAWINGS

FIG. 1 is a schematic drawing of a prior art filter;

FIG. 2 is a schematic diagram illustrating a digital filter realized inaccordance with the invention; and

FIG. 3 illustrates an embodiment of the invention.

FIG. 4 is a graph illustrating the time relationships between thesignals of the filter.

In all prior art implementations of a digital filter using the deltacoding scheme, the computation of the value of each output signal sampley(t) has always amounted to solving Eq. (3) above wherein the inputsignal x(t) is delta coded. With this coding, the values of inputsamples

    x.sub.(t.sbsb.o), x.sub.(t.sbsb.o.sub.-T), . . . , x.sub.(t.sbsb.o.sub.-nT)

can only be equal to +1 or -1. However, the values of h_(o), h₁, . . . ,h_(n) are determined by using the binary PCM coding scheme and eachvalue comprises several bits. FIG. 1 illustrates the principle of thisoperation for n=2. The analog input signal x(t) is delta coded in coder1 and the samples thus obtained on line 2 are applied to a shiftregister 3 designed to provide at its outputs 4 and 5, the delta valuesfor samples x(t-T) and x(t-2T). Each of the samples on lines 2, 4 and 5,the value of which is equal to either +1 or -1, is then multiplied by afilter coefficient of value h_(o) =a₁, h₁ =a₂ or h₂ =a₃. The results ofthese operations are algebraically added together in an adder 6 toprovide a sample of output signal y (t ). Since the coefficients are PCMcoded, the output samples is coded in differential PCM(ΔPCM). Itsconversion to analog form requires a decoding operation performed indecoder 7. Since signal x(t) is not PCM coded at the input and signaly(t) is not PCM coded at the output of the filter, these signals canundergo no operation involving the use of such a code unlessintermediate recoding operations are performed.

In the present invention, any one of a series of PCM operationsassociated with a complex processing of signal x(t) can be performedbefore the signal is applied to the filter, while retaining theadvantages of delta filtering.

FIG. 2 illustrates in schematic form the method of the invention. Asshown, an input analog signal x(t) is given any needed processing and isPCM coded in coder 8 and its samples each in the form of a sequence ofbinary signals, are then applied over line 9 to a tapped shift register10 which holds the samples for weighting with the filter coefficients.The latter are obtained by means of a differential or delta coding ofthe desired impulse response h(t) of the filter. Since expression (1) iscommutative, the operations performed on x(t) can just as well beperformed on h(t). The coefficient terms can therefore be coded usingthe differential PCM (ΔPCM) coding scheme, instead of such a coding ofsignal x(t), without the result of the filtering operation beingmodified as a result thereof. It should be noted that, in this codingscheme, several bits (PCM) may still be used to represent the signalamplitude. However, if a 1-bit code (Δcode) is used, it becomes possibleto simplify the weighting process, although a much larger number ofcoefficients must be used to properly define the filter than in theexample of FIG. 1. The weighted samples are to be added together inadder 11 to provide the required ΔPCM coded samples of y(t). Theseoutput samples of adder 11 are then decoded in decoder 12 to provide thefiltered analog signal on line 13.

Despite these advantages, the differential mode of coding illustrated inFIG. 2 may be considered impractical since a filter requiring, say, tentaps in an all-PCM approach, or even in a conventional delta approach asabove mentioned, would now require as much as ten times as many. Inaddition, shift register 10 would have to be up to ten times larger thanin either of the other approaches.

This difficulty can be somewhat overcome by taking advantage of the factthat the PCM or delta coded samples are stored in the shift register 10at regular intervals related to the sampling rate T. Accordingly, inorder for the device of FIG. 2 to have the same capabilities as that ofFIG. 1, no more than three PCM coded samples of x(t) need be shiftingthrough shift register 10 at any one time. Since each of these sampleswill pass several taps during a sampling interval, both the number oftaps used for weighting and the length of the shift register can besubstantially reduced.

Assuming, for example, that the selected sampling and weighting rateusing the delta coding scheme is four times higher than the rate atwhich the samples are received at the input 9 of the filter, twelvecoefficients, b₁ -b₁₂, would be required. In other words, the filteredoutput signal samples y(t) to be generated between instants t and t+Tmust satisfy the following expressions:

    y.sub.1 (t) = b.sub.1 x.sub.(t) + b.sub.5 x.sub.(t.sub.-T) + b.sub.9 x.sub.(t.sub.-2T)

    y.sub.2 (t) = b.sub.2 x.sub.(t) + b.sub.6 x.sub.(t.sub.-T) + b.sub.10 x.sub.(t.sub.-2T)

    y.sub.3 (t) = b.sub.3 x.sub.(t) + b.sub.7 x.sub.)t.sub.-T) + b.sub.11 x.sub.(t.sub.-2T)

    y.sub.4 (t) = b.sub.4 x.sub.(t) + b.sub.8 x.sub.(t.sub.-T) + b.sub.12 x.sub.(t.sub.-2T)                                         (4)

the next samples to be generated, i.e. in the interval from t+T to t+2T,must be:

    y.sub.1 (t+T) = b.sub.1 x.sub. (t.sub.+T) + b.sub.5 x.sub.(t) + b.sub.9 x.sub.(t.sub.+T)

    y.sub.2 (t+T) = b.sub.2 x.sub.(t.sub.+T) + b.sub.6 x.sub.(t) + b.sub.10 x.sub.(t.sub.+T)

    y.sub.3 (t+T) = b.sub.3 x.sub.(t.sub.+T) + b.sub.7 x.sub.(t) + b.sub.11 x.sub.(t.sub.+T)

    y.sub.4 (t+T) = b.sub.4 x.sub.(t.sub.+T) + b.sub.8 x.sub.(t) + b.sub.12 x.sub.(t.sub.+T)

the samples of x can therefore be weighted in groups of three, providedthe weighting operations are performed four times before a new PCM codedsample is received at the input 9 of the filter. Thus, theabove-mentioned disadvantagees of the invention can be overcome byrepeating the weighting operations several times between two consecutiveoccurrences of data at the input of the filter. A device realized inaccordance with the diagram of FIG. 3 may be used to this end.

As shown in FIG. 3, the filter input lines 2 are connected to a set ofAND gates A1 to A4 which open when a control signal T2 is present duringthe time a sample value is present at input 9. The output of each ofthese gates is connected to the inputs of a set of four shift registersSR1 to SR4 with three bit positions each, through an associated one offour OR circuits 01 to 04. The output bits from each of these registersis sent back over a bus 12 to the input thereof through one of four ANDgates A'1 to A'4 which are opened when T2 is not present, i.e. at alltimes except when a new input sample is being entered into the shiftregisters, and the output is simultaneously applied to a correspondingpair of four pairs of AND gates A5 to A8 and A'5 to A'8. The outputs ofeach of these pairs of AND gates are respectively applied to the inputsof one of four OR circuits O5 to O8, either directly from gates A5 to A8or from gates A'5 to A'8 through one of the inverters I1 to I4,associated therewith. The outputs of OR O5 to O8 are in turn applied toone set of inputs of an accumulator which includes an adder 13 and aregister 14, the output of which is fed back over a bus 15 to the otherinputs of the adder 13. The arrangement further includes one bit wideread-only storage 16, the output of which is directly connected to thecontrol inputs of AND gates A5 to A8 and is connected through aninverter I5 to the control inputs of AND gates A'5 to A'8. The output ofI5 is also connected to one of the inputs of the low order of adder 13.A modulo 13 counter 17 is provided to address the storage 16 containingcoefficients b1 to b12 which are equal to ± 1 and are stored atconsecutive addresses in accordance with the sequence b₉, b₅, b₁, b₁₀,b₆, b₂, b₁₁, b₇, b₃, b₁₂, b₈, b₄. The last counter position (13) doesnot correspond to a valid address but is needed for timing and shiftingpurposes only.

At the instant the generation of sample y(t) of expression (4) begins,see also the timing diagram of FIG. 4, those positions of registers SR1to SR4 which are closest to the inputs contain the bits of the value ofthe input sample x(t). The other positions contain the bits of thevalues of samples x.sub.(t_(-T)) in the middle position and x_(t)_(-2T)) in the bottom position. The first rise of shift pulse T1,counter 17 =0, causes the bits of word x.sub.(t_(-2T)) to be shifted outto the inputs of the pairs of AND gates A5 to A8 and A'5 to A'8. Shiftpulse T1 has also incremented the count value in counter 17 to 1 and thecoefficient b₉ is read out of storage. If the value of the coefficientbeing read is equal to +1, AND gates A5 to A8 are opened and the valueof word x.sub.(t_(-2T)) is fed to added 13 of the accumulator. If thecoefficient b₉ is equal to -1, then x.sub.(t_(-2T)) must be inverted. Itwill first be noted that the output of inverter I5 controls AND gatesA'5 to A'8 to open, resulting, because of the presence of inverters I1to I4, in the entry of the complements of the bits of signalx.sub.(t_(-2T)) being fed to the adder 13 of the accumulator. This,however, will not suffice to cause the value x.sub.(t_(-2T)) to becompletely inverted when the PCM samples of input signal x(t) are codedusing the so-called two's complement code. A value of +1 must be addedto the bits which have been inverted to complete the required valueinversion. A free low order input of adder 13 is used for this entry.The output of inverter I5 is connected to the carry input of the stagethereof that processes the lowest order bit. The computed word b₉.sup..x .sub.(t_(-2T)) passes through the adder unchanged and is stored inregister 14 under control of a timing signal T4 determined as the ANDfunction of signals T1 and T2 as indicated on the bottom line of FIG. 4.While it was applied to the couples of gates A5 to A8 and A'5 to A'8,the word x.sub.(t_(-2T)) was also returned over a bus 12 to the set ofAND gates A'1 to A'4 on the inputs of shift registers SR1 to SR4 and,since T2 was then equal to zero, was again stored therein. The contentsof the shift registers SR1 to SR4 are now, from the input to the outputof the registers, x.sub.(t_(-2T)), x.sub.(t) and x.sub.(t_(-T)).

When the next T1 pulse occurs, x.sub.(t_(-T)) is simultaneously appliedto the inputs of said pairs of gates A5 to A8 and A'5 to A'8 and to therecirculation loop 12 of the registers SR1 to SR4. Since T2 is stilldown, x.sub.(t_(-T)) is stored in the shift registers again, with T1causing the contents to be shifted. At the same time, the count value ofcounter 17 is incremented by T1, so that coefficient b₅ is read out ofROS 16, and the term b₅.sup.. x .sub.(t_(-T)) computed as before isapplied to the input of addr ADD together with the value already inregister 14, namely b₉.sup.. x .sub.(t_(-2T)). The adder 13 performs theoperation b₉.sup.. x .sub.(t_(-2T)) + b₅.sup.. x .sub.(t_(-T)) andsignal T4 then stores the result in register 14. At the next T1 pulse,b₁.sup.. x .sub.(t) is calculated and added to the previous result fromregister 14. After this addition and entry of the value into register14, the increment y₁ (t) of the ΔPCM coded output signal is present inregister 14. This increment is sent through AND gate A13 which is openedby the signal T3 and register 14 is reset when the T3 signal falls toits low level. This shows that the output signal y(t) is obtained at asampling rate higher than 1/T (in this example, four times higher). Theabove process is repeated three more times to obtain all increments y₁(t), y₂ (t), y₃ (t), and y₄ (t) in four circulations, i.e.:

    y.sub.1 (t) = b.sub.9.sup.. x.sub.(t.sub.-2T) + b.sub.5.sup.. x.sub.(t.sub.-T) +b.sub.1.sup.. x.sub.(t)                 (a)

    y.sub.2 (t) = b.sub.10.sup.. x.sub.(t.sub.-2T) + b.sub.6.sup.. x.sub.(t.sub.-T) + b.sub.2.sup.. x.sub.(t)                (b)

    y.sub.3 (t) = b.sub.11.sup.. x.sub.(t.sub.-2T) + b.sub.7.sup.. x.sub.(t.sub.-T) + b.sub.3.sup.. x.sub.(t)                (c)

    y.sub.4 (t) = b.sub.12.sup.. x.sub.(t.sub.-2T) + b.sub.8.sup.. x.sub.(t.sub.-T) + b.sub.4.sup.. x.sub.(t)                (d)

A dΔ decoder 18 is provided at the output of the filter to convert theΔPCM coded signals y₁ (t) to y₄ (t) to an analog form. A suitabledecoder is described, for example, in a paper entitled "Delta ModulationCode for Transmission and Switching Applications" by R. R. Laane and B.I. Murphy, in the Bell System Technical Journal, pp. 1013-1031,July-August 1970.

To complete the above description, it should be stated that during thelast circulation, namely (d), T2 becomes positive while B₁₂ .sup..x.sub.(t_(-2T)) is being determined and prevents the reentry of thevalue x.sub.(t_(-2T)) which is replaced in shift registers SR1 to SR4 bythe next sample x.sub.(t_(+T)) received at the input 2 of the filter asshown on the input representing line of FIG. 4. The latter sample isthen shifted twice through the shift registers while b₈.sup..x.sub.(t_(-T)) and then b₄.sup.. x.sub.(t) are being computed, andfinally appears at the output of SR3. Another T1 pulse will shift theX.sub.(t_(+T)) value back to the input end of the shift registers to setthe samples into the processed arrangement x.sub.(t_(+T)), x.sub.(t) andx.sub.(t_(-T)) to start a new cycle. During this T1 pulse, no new valueis entered from adder 13 into register 14 since there is no T4 pulse andin effect, this operation is solely a shift pulse for the shiftregisters and counter 17. The computation of y.sub.(t_(+T)) is theninitiated after counter C has been reset to zero under the control ofpulse T2.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

What is claimed is:
 1. A digital filter wherein each consecutive sampleof an incoming signal is digitally coded with negative amplitudes beingcoded in a "two-complement" code, said filter including:a shift registerto store the values of the last n samples of said incoming signal; asource of clock signals to shift said samples through said shiftregister, gates on the input of said shift register normally activatedby one of said clock signals to feed back the output of said shiftregister to the input thereof to recirculate said stored values; othergates on the input of said shift register activated by the complement ofsaid one of said clock signals to feed the value of a new sample of saidinput signal to the input of said shift register; an accumulator to sumup digitally coded values; a read only storage with each storage addressset to represent only a positive or a negative value corresponding todelta coding of the impulse response of said digital filter; a clocksignal driven cyclic addressing means for said read only storage toprovide sequential positive or negative value signals; gates controlledby said sequential positive or negative value signals to pass the oldestvalue stored in said shift register directly or complementallyrespectively to an input of said accumulator; and output gates toperiodically gate out the accumulated values as a filtered set of outputsignals.
 2. A digital filter as in Claim 1 in which said accumulator tosum up digitally coded values comprises:an adder having on each of theinput circuits for one factor, one of said controlled gates to pass theoutput of said shift register to said inputs and a second one of saidcontrolled gates to pass said output through a bit inverter and thenceto said inputs; a storage register to receive the output of said adder;circuits connecting the output of said storage register as a secondfactor input of said adder; and an output circuit receiving selectedoutput values from said storage register.
 3. A digital filter as set outin claim 2 including:a carry input to said adder; an inverter activatedwhen a negative value signal coefficient is read from said storage; andconnections from the output of said inverter to activate said carryinput and said set of second gates.